Semiconductor fabrication of integrated circuits continues to supply vital equipment to a myriad of technological fields. Integrated circuits continue to grow increasingly complex and densely filled with components. Accordingly, manufacturing these integrated circuits becomes more difficult. Makers of integrated circuits spend considerable effort increasing the yield of the fabrication process as well as increasing the reliability of its output. The metal interconnect system employed during the manufacturing of large and very large scale integrated circuits is of special concern to the yield and reliability of these products.
During the process of creating a semiconductor-based integrated circuit, various layers of semiconductors, metals, insulators, and other materials are deposited and patterned in layers on top of each other. Masks are employed to control the process and patterned to create connections between circuit elements. These connections can be either horizontal or vertical in nature. The horizontal interconnect layers are joined together by vertical connections called vias. These connections may be made between metal layers or from a metal layer to a semiconductor layer, in which case the connection is commonly referred to as a contact. All vertical interconnects will be hereafter referred to as vias.
The complexity of modern integrated circuits has been increasing due to both the further miniaturization of the circuits and also to the increase in the number of elements included in these systems and circuits. As the circuits become more complex, more layers are required to connect the ever increasing number of circuit elements. The increasing number of layers may also increase the number of horizontal interconnecting wires, which may add parasitic resistance. To improve the wire resistance, a horizontal interconnection wire may be made from polysilicon on top of which a silicide layer is formed. Silicides on polysilicon forms salicided polysilicon and is used to minimize a parasitic resistance and known to be used for gate structures in MOSFET devices (so-called polycide gate), on source-drain connections or as local interconnection. It provides for a low resistance, good process compatibility with silicon and good contact properties to other materials. It can be easily dry etched and provides for little or no electromigration.
However, an error in the manufacturing of an integrated circuit can amongst others be caused by a faulty or improper formation of the silicide layer, which could degrade the flow of electricity on a horizontal wire, or cause a component to malfunction. Further, an improper silicide layer may not cause the chip to fail immediately, but may degrade over time in the field, creating a reliability concern.
A semiconductor manufacturer can increase a process's ability to produce reliable and consistent interconnects by using a test structure containing a large chain of horizontal and vertical interconnects. This structure is typically used during the process development phase, and aids the process engineers in evaluating the robustness of the interconnect system. After the initial process development work, the integrated circuits rather than test structures are used to monitor the health of the process technology by metrics such as test yield and reliability experiments. Using the large integrated circuits for monitoring the health of the process can be problematic. When the product fails a test program, it is very difficult to determine the exact location and root cause of the failure because of the shear complexity of the device. A process using a test structure consisting of a chain of horizontal metal and vertical vias might be impractical because it does not pinpoint which specific element in the interconnect system caused the failure.
One solution to make the via and horizontal interconnect manufacturing process more robust is to design a two dimensional array of vias where it is possible to test individual vias through a decoding scheme utilizing transistors as switches to turn on and off connection paths to be tested. However, transistors occupy a significant amount of silicon area so as to limit how many vias and horizontal interconnects can be placed within the test structure. Further, a significant amount of current may be necessary to accurately measure the actual via and horizontal interconnect resistance. Transistors are relatively limited in the current they can carry. Thus, there exists a need for an improved process to monitor an interconnect system in a semiconductor manufacturing process in particular to monitor the salicide process for interconnect purposes.